(a) Field of the Invention
The present invention relates to a power factor correction circuit, and more particularly, a power factor correction circuit for compensating distortion of an input current.
(b) Description of the Related Art
Due to current harmonic limitation standards, such as the EN61000-3-2 standard, power factor correction circuits are used in switching mode power supply (SMPS) devices. The SMPS device is used to convert an input supply voltage into direct output voltages for power supply devices typically found in, for example, mobile telephones and laptop computers. In the SMPS device, a power factor correction circuit is used for compensating power factors by controlling an input current to follow the input voltage. That is, the power factor correction circuit controls the input current to follow the external input voltage and outputs a constant direct current (DC) voltage converted from the input alternating current (AC) voltage.
The power factor correction circuit typically includes an inductor, and has various modes depending on the state of the current flowing through the inductor. For example, the current flows continuously in a continuous conduction mode, and flows discontinuously in a discontinuous conduction mode since the current flowing through the inductor reaches 0A at some point. In addition, in a critical conduction mode operating between the continuous and discontinuous conduction modes, the current flowing through the inductor is increased after it has reached 0A. The ST L6561 is a well-known power factor correction integrated circuit (IC) that operates in the critical conduction mode. Other IC power factor correction circuits include FAN7527B, TDA4862, TDA4863, MC33260, MC33262, UC3852, and SG6561.
An operation of the prior art critical conduction mode power factor correction circuit and a total harmonic distortion (THD) caused by the operation of the circuit will be described with reference to FIG. 1 to FIG. 3. FIG. 1 is a schematic diagram of a prior art critical conduction mode power factor correction circuit. FIG. 2 is a waveform diagram of a current IL1 flowing through an inductor L1, a voltage VZCD at a secondary-side winding wire L2, a gate signal input to a switch Qsw, and an actual current in the power factor correction circuit shown in FIG. 1. FIG. 3 is a waveform diagram of an input current in the prior art power factor correction circuit shown in FIG. 1.
As shown in FIG. 1, a bridge diode BD full-wave rectifies the input AC voltage, resistors R1 and R2 sense the full-wave rectified voltage, and a multiplier 20 receives it. The sensed full-wave rectified voltage input to the multiplier 20 is multiplied by the output of an amplifier Amp1, and this product is input to an inverting terminal (−) of a comparator Amp2. A current flowing through a switch Qsw is sensed by a resistor Rsense, and a sensed voltage Vsense is input to a non-inverting terminal (+) of the comparator Amp2. The comparator Amp2 compares an output of the multiplier 20 with the sensed voltage Vsense, and outputs a signal for turning off the switch Qsw when the current flowing through the switch Qsw meets a reference current output from the multiplier 20.
A reset terminal of a flip flop 10 receives the signal for turning off the switch Qsw. When the reset terminal receives the signal, the flip flop FF outputs a Low signal to an output terminal Q, and turns off the switch Qsw. The secondary-side winding wire L2 of the inductor L1 senses when a current flowing to the inductor L1 becomes 0, at which point a set terminal of the flip flop 10 is provided with a High signal. The High signal is then output to the Q output terminal, causing the switch Qsw to turn on.
As described, the input current follows the input voltage since the switch Qsw is turned on when the current flowing to the inductor L1 becomes 0, and the switch Qsw is turned off when the current flowing to the inductor L1 meets the reference current input to the inverting terminal (−) of the comparator Amp2. Accordingly, the power factor correction circuit operates in the critical conduction mode.
The input current must be in the form of a sine waveform corresponding to the input voltage to the power factor correction circuit. The sine waveform, however, is not exact since there is a delay in sensing the point when the current through the inductor L1 becomes 0 (hereinafter, the delay will be referred to as a “0 current sensing delay”). The critical conduction mode power factor correction circuit senses the point of time when the current flowing to the inductor L1 through the secondary-side winding wire L2 becomes 0, as shown in FIG. 1. FIG. 2 shows a case when there is a 0 current sensing delay in turning on the switch Qsw after the current IL1 of the inductor L1 becomes 0. Referring to FIG. 2, when the switch Qsw is turned on, the current IL1 is linearly increased, and a voltage VZCD at the secondary-side winding wire L2 becomes −n*Vin (where n denotes a transformer turns ratio). When the switch Qsw is turned off, the current IL1 is reduced with a negative slope and the voltage V ZCD becomes n*(Vout-Vin).
At this time, the switch must be turned on when the current IL1 becomes 0. However, the current IL1 has a negative value since resonance current is formed during the 0 current sensing delay between a junction capacitor Coss of a metal-oxide semiconductor field-effect transistor (MOSFET) used as the switch and the inductor L1. That is, the current IL1 has a negative value since a voltage at the capacitor Coss becomes a voltage Vout and the voltage Vout is set higher than a voltage Vin when the switch Qsw is turned off. The capacitor Coss is coupled to the switch Qsw in parallel, and a diode Db is a body diode. The switch Qsw is turned on since the High signal is input to the set terminal S of the flip flop 10 when the current IL1 is reduced to the negative current and the voltage VZCD is less than the reference voltage Vth.
As shown in FIG. 2(d), due to the negative current, a current actually flowing to the inductor L1 becomes a current c obtained by subtracting a negative current b from a desired current a. In addition, a peak value of the negative current is given in Equation 1.
                              I          NEG                ∝                              Vout            -            Vin                                              L1                              C                oss                                                                        (        1        )            where Vout denotes an output voltage, and Vin denotes a full-wave rectified input voltage. As shown in Equation 1, the peak value INEG of the negative current is in proportion to a difference between the output voltage Vout and the input voltage Vin. The peak value INEG of the negative current is inversely proportional to the input voltage Vin since the inductor L1, capacitor Coss, and voltage Vout have fixed values. Accordingly, the current IL1 is further reduced as the input voltage Vin decreases. That is, the peak value INEG of the negative current is further increased at a point of time when the input voltage Vin becomes 0V. Accordingly, a zero crossing distortion in the input current occurs, as shown in FIG. 3. The input current shown in FIG. 3 is a current before being rectified, and is the current corresponding to the input AC voltage.
U.S. Pat. No. 6,128,205 discloses a method for decreasing the zero crossing distortion. In this patent, information on a rectified input voltage as a reference for turning off a switch is modified to increase the current IL1 flowing to the inductor L1 when the input voltage becomes 0. That is, a voltage at a resistor R2 is clamped by an additional circuit and is input to the multiplier 20 in FIG. 2. Accordingly, the zero crossing distortion is compensated by the modified and rectified input voltage. However, in this method, an additional circuit is required, including a plurality of resistors to modify the rectified input voltage, which results in both high cost and high power consumption.
The information disclosed above is only for enhancement of understanding of the background of the invention, and may contain information that does not constitute the prior art.